LPC2923FBD100,551 NXP Semiconductors, LPC2923FBD100,551 Datasheet - Page 51

• Manufacturer Part Number: LPC2923FBD100,551
• Description: IC ARM9 MCU FLASH 256KB 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2900r

Specifications of LPC2923FBD100,551

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 125MHz
• Connectivity: CAN, I²C, LIN, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 16x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC29
• Core: ARM968E-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935287115551

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
6.16.1 Functional description
6.16 Vectored interrupt controller
Table 29.
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
The LPC2921/2923/2925 contains a very flexible and powerful Vectored Interrupt
Controller (VIC) to interrupt the ARM processor on request.
The key features are:
The Vectored Interrupt Controller routes incoming interrupt requests to the ARM
processor. The interrupt target is configured for each interrupt request input of the VIC.
The targets are defined as follows:
Branch clock name
CLK_UART0
CLK_UART1
CLK_SPI0
CLK_SPI1
CLK_SPI2
CLK_TMR0
CLK_TMR1
CLK_TMR2
CLK_TMR3
CLK_ADC1
CLK_ADC2
CLK_USB
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Level-active interrupt request with programmable polarity.
56 interrupt-request inputs.
Software-interrupt request capability associated with each request input.
Interrupt request state can be observed before masking.
Software-programmable priority assignments to interrupt requests up to 15 levels.
Software-programmable routing of interrupt requests towards the ARM-processor
inputs IRQ and FIQ.
Fast identification of interrupt requests through vector.
Support for nesting of interrupt service routines.
Target 0 is ARM processor FIQ (fast interrupt service).
Target 1 is ARM processor IRQ (standard interrupt service).
Branch clock overview
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 14 April 2010
Base clock
BASE_UART_CLK
BASE_UART_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_TMR_CLK
BASE_ADC_CLK
BASE_ADC_CLK
BASE_USB_CLK
BASE_SPI_CLK
BASE_SPI_CLK
BASE_SPI_CLK
…continued
ARM9 microcontroller with CAN, LIN, and USB
LPC2921/2923/2925
Implemented switch on/off
mechanism
WAKE-UP
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AUTO
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© NXP B.V. 2010. All rights reserved.
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RUN
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