LPC2923FBD100,551 NXP Semiconductors, LPC2923FBD100,551 Datasheet - Page 48

• Manufacturer Part Number: LPC2923FBD100,551
• Description: IC ARM9 MCU FLASH 256KB 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2900r

Specifications of LPC2923FBD100,551

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 125MHz
• Connectivity: CAN, I²C, LIN, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 16x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC29
• Core: ARM968E-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935287115551

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
6.15.4.1 Functional description
6.15.4.2 Pin description
Each reset output is defined as a combination of reset input sources including the external
reset input pins and internal power-on reset, see
this table form a sort of cascade to provide the multiple levels of impact that a reset may
have. The combined input sources are logically OR-ed together so that activating any of
the listed reset sources causes the output to go active.
Table 27.
The RGU module in the LPC2921/2923/2925 has the following pins.
RGU pins.
Reset output
POR_RST
RGU_RST
PCR_RST
COLD_RST
WARM_RST
SCU_RST
CFID_RST
FMC_RST
EMC_RST
GESS_A2V_RST
PESS_A2V_RST
GPIO_RST
UART_RST
TMR_RST
SPI_RST
IVNSS_A2V_RST
IVNSS_CAN_RST
IVNSS_LIN_RST
MSCSS_A2V_RST
MSCSS_PWM_RST
MSCSS_ADC_RST
MSCSS_TMR_RST
I2C_RST
QEI_RST
DMA_RST
USB_RST
VIC_RST
AHB_RST
•
Register write-protection mechanism to prevent unintentional resets
Reset output configuration
All information provided in this document is subject to legal disclaimers.
Reset source
power-on reset module
POR_RST, RST_N pin
RGU_RST, WATCHDOG PCR internal; source for COLD_RST
PCR_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
COLD_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
WARM_RST
Rev. 03 — 14 April 2010
ARM9 microcontroller with CAN, LIN, and USB
all CAN modules including Acceptance filter
all LIN modules
all timer modules in MSCSS
Quadrature encoder
Parts of the device reset when activated
LP_OSC; source for RGU_RST
RGU internal; source for PCR_RST
parts with COLD_RST as reset source below
parts with WARM_RST as reset source below
SCU
CFID
embedded Flash Memory Controller (FMC)
embedded SRAM-Memory Controller
GeSS AHB-to-APB bridge
PeSS AHB-to-APB bridge
all GPIO modules
all UART modules
all timer modules in PeSS
all SPI modules
IVNSS AHB-to-APB bridge
MSCSS AHB to APB bridge
all PWM modules
all ADC modules
all I
DMA controller
USB controller
Vectored Interrupt Controller (VIC)
CPU and AHB Bus infrastructure
LPC2921/2923/2925
Table
2
C modules
27. The first five resets listed in
Table 28
© NXP B.V. 2010. All rights reserved.
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