M3062GF8NGP#U5 Renesas Electronics America, M3062GF8NGP#U5 Datasheet - Page 182

• Manufacturer Part Number: M3062GF8NGP#U5
• Description: MCU 3V 64K PB FREE 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M3062GF8NGP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Electrical characteristics
Rev.1.1
Switching characteristics (referenced to V
85
Table 1.26.23. Memory expansion and microprocessor modes
Note 2: Specify a product of –40°C to 85°C to use it.
Note 1: Calculated according to the BCLK frequency as follows:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
h(WR-CS)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
h(WR-DB)
d(AD-ALE)
h(ALE-AD)
d(AD-RD)
d(AD-WR)
dZ(RD-AD)
d(BCLK-ALE)
h(BCLK-ALE)
Symbol
o
C (Note 2), CM15 = “1” unless otherwise specified)
td(AD – ALE) =
th(RD – AD) =
th(WR – AD) =
th(RD – CS) =
th(WR – CS) =
td(DB – WR) =
th(WR – DB) =
Address output delay time
Address output hold time (WR standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (WR standard)
ALE signal output hold time (BCLK standard)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
WR signal output delay time
Data output hold time (BCLK standard)
Data output delay time (WR standard)
ALE signal output delay time (BCLK standard)
ALE signal output delay time (Address standard)
ALE signal output hold time(Address standard)
Post-address RD signal output delay time
Post-address WR signal output delay time
Address output floating start time
(when accessing external memory area with wait, and select multiplexed bus)
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
10
Parameter
10
10
10
10
10
10
9
9
9
9
9
9
9
X 3
– 80
– 45
[ns]
[ns]
[ns]
[ns]
[ns]
[ns]
[ns]
CC
= 3V, V
Measuring condition
SS
Figure 1.26.1
= 0V at Topr = – 20
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
Min.
– 4
40
4
4
4
0
0
0
0
Standard
o
C to 85
Max.
60
60
60
60
80
60
8
M3062GF8NFP/GP
o
Mitsubishi microcomputers
C / – 40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
o
C to
179