M3062GF8NGP#U5 Renesas Electronics America, M3062GF8NGP#U5 Datasheet - Page 56

MCU 3V 64K PB FREE 100-LQFP

M3062GF8NGP#U5

Manufacturer Part Number
M3062GF8NGP#U5
Description
MCU 3V 64K PB FREE 100-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M3062GF8NGP#U5

Core Processor
M16C/60
Core Size
16-Bit
Speed
10MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M3062GF8NGP#U5M3062GF8NGP
Manufacturer:
MITSUBISHI
Quantity:
20 000
Company:
Part Number:
M3062GF8NGP#U5M3062GF8NGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M3062GF8NGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Interrupt
Rev.1.1
Table 1.11.5. Time required for executing the interrupt sequence
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 1.11.5. Time required for executing the interrupt sequence
Table 1.11.6. Relationship between interrupts without interrupt priority levels and IPL
Interrupt vector address
Variation of IPL when Interrupt Request is Accepted
BCLK
Address bus
Data bus
R
W
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.11.5.
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.11.6 is set in the IPL.
Watchdog timer, NMI
Reset
Other
Odd (Note 2)
Odd (Note 2)
interrupt or of a single-step interrupt.
Interrupt sources without priority levels
Even
Even
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
1
_______
Address
0000
information
2
Stack pointer (SP) value
Interrupt
3
4
Even
Even
Odd
Odd
Indeterminate
________
Indeterminate
5
Indeterminate
6
7
16-Bit bus, without wait
8
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
SP-2
9
contents
SP-2
10
SP-4
11
contents
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Value set in the IPL
SP-4
12
Not changed
13
vec
contents
vec
7
0
8-Bit bus, without wait
14
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
M3062GF8NFP/GP
vec+2
15
Mitsubishi microcomputers
contents
vec+2
16
17
PC
18
53

Related parts for M3062GF8NGP#U5