D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 143

IC H8S/2312S MCU ROMLESS 100QFP

D12312SVF20V

Manufacturer Part Number
D12312SVF20V
Description
IC H8S/2312S MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12312SVF20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12312SVF20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.1
5.1.1
The chip controls interrupts by means of an interrupt controller. The interrupt controller has the
following features. The available interrupt sources are external interrupts (NMI, IRQ7 to IRQ0)
and internal interrupts (43 sources).
• Two interrupt control modes
• Priorities settable with IPRs
• Independent vector addresses
• Nine external interrupt pins
• DTC control
⎯ Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
⎯ Interrupt priority registers (IPRs) are provided for setting interrupt priorities. Eight priority
⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7
⎯ DTC activation is controlled by means of interrupts
in the system control register (SYSCR)
levels can be set for each module for all interrupts except NMI
the source to be identified in the interrupt handling routine
edge can be selected for NMI
to IRQ0
Overview
Features
Section 5 Interrupt Controller
Rev.7.00 Feb. 14, 2007 page 109 of 1108
Section 5 Interrupt Controller
REJ09B0089-0700

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