D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 457

• Manufacturer Part Number: D12312SVF20V
• Description: IC H8S/2312S MCU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVF20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other
registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for
RSTCSR.
11.3
11.3.1
To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent
TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
This ensures that TCNT does not overflow while the system is operating normally. If TCNT
overflows without being rewritten because of a system crash or other error, the WDTOVF signal *
is output. This is shown in figure 11.4. This WDTOVF signal * can be used to reset the system.
The WDTOVF signal * is output for 132 states when RSTE = 1, and for 130 states when RSTE =
0.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the chip
internally is generated at the same time as the WDTOVF signal * . The internal reset signal is
output for 518 states.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
Note: * The WDTOVF function is not available in the F-ZTAT versions.
Writing 0 to WOVF bit
Writing to RSTE bit
Operation
Operation in Watchdog Timer Mode
Address: H'FFBE
Address: H'FFBE
Figure 11.3 Writing to RSTCSR
15
15
H'A5
H'5A
Rev.7.00 Feb. 14, 2007 page 423 of 1108
8 7
8 7
Section 11 Watchdog Timer
Write data
H'00
REJ09B0089-0700
0
0