D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 624
![IC H8S/2312S MCU ROMLESS 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
D12312SVF20V
Manufacturer Part Number
D12312SVF20V
Description
IC H8S/2312S MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVF20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12312SVF20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 17 ROM
17.6.1
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315
F-ZTAT, or H8S/2314 F-ZTAT chip’s pins have been set to boot mode, the boot program built
into the chip is started and the programming control program prepared in the host is serially
transmitted to the chip via the SCI. In the chip, the programming control program received via the
SCI is written into the programming control program area in on-chip RAM. After the transfer is
completed, control branches to the start address of the programming control program area and the
programming control program execution state is entered (flash memory programming is
performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 17.9, and the boot program mode
execution procedure in figure 17.10.
Rev.7.00 Feb. 14, 2007 page 590 of 1108
REJ09B0089-0700
Boot Mode
Host
Figure 17.9 System Configuration in Boot Mode
Verify data transmission
Write data reception
Chip
RxD1
TxD1
SCI1
Flash memory
On-chip RAM
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