R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 1006

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I2C Bus Interface 2 (IIC2)
16.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
Page 976 of 1372
(master output)
(master output)
(slave output)
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS in ICCRA and TDRE in ICSR
are set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by clearing TDRE after writing transmit data to ICDRT every time
TDRE is set.
with TDRE = 1. When TEND is set, clear TEND.
User
processing
ICDRS
ICDRR
SCL
SDA
SDA
RCVD
RDRF
Slave Transmit Operation
Data n-1
Figure 16.8 Master Receive Mode Operation Timing 2
9
A
[5] Read ICDRR
Data n-1
after setting RCVD.
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
4
[6] Issue stop
Bit 3
5
condition
Bit 2
6
Bit 1
7
[7] Read ICDRR
H8S/2426, H8S/2426R, H8S/2424 Group
and clear RCVD
Bit 0
Data n
8
A/A
9
REJ09B0466-0350 Rev. 3.50
Data n
[8] Set slave
receive mode
Jul 09, 2010