R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 701

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
• PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A*
• Modes 1, 2, 4, and 7 (EXPE = 1)
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
OEE
RMTS2 to
RMTS0
WAITE
WAITS
SSU settings
PF0DDR
Pin function
OEE
RMTS2 to
RMTS0
WAITE
WAITS
SSU settings
PF0DDR
Pin function
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR*
CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and
EXTRGS in ADCR_0 of the ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4,
bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
PF0 input
PF0 input
(1) in table below
(1) in table below
0
0
output
PF0
output
1
PF0
1
SCS0-C
input*
below
(2) in
table
SCS0-C
⎯
input*
0
0
below
(2) in
table
⎯
0
0
3
Settings other than that for areas 2 to 5 as DRAM
3
SCS0-C
below
(4) in
table
I/O*
0
SCS0-C
below
(4) in
table
I/O*
5
0
5
SCS0-C
output*
below
(3) in
table
⎯
5
SCS0-C
output*
ADTRG0-B input*
(H8S/2424 Group)
below
(3) in
table
ADTRG0-B input*
4
⎯
WAIT-A
4
input
⎯
⎯
⎯
0
0
1
WAIT-A
input
⎯
⎯
0
PF0 input
below
2
(1) in
table
2
0
PF0 input
below
(1) in
table
0
prohibited
Setting
⎯
1
1
prohibited
Setting
1
⎯
SCS0-C
1
1
input*
below
(2) in
table
0
1
3
Section 10 I/O Ports
SCS0-C
input*
below
(2) in
table
prohibited
(3) (4) in
Setting
Page 671 of 1372
0
below
table
5
, bits MSS,
0
3
prohibited
(3) (4) in
Setting
Areas 2 to
output*
below
table
DRAM
space
OE-A
5 are
0
⎯
⎯
⎯
⎯
1
*
6