R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 1126

MCU 256KB FLASH 64K 144-LQFP

R4F24269NVFQV

Manufacturer Part Number
R4F24269NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24269NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24269NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
R4F24269NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 21 Flash Memory
21.5
The status register indicates the state of flash memory operation and whether erasure or
programming has ended successfully or with an error. The status register contents can be read
through the FMRDY, FMPRSF, and FMERSF bits in FLMSTR.
Table 21.6 shows the status register.
In the EW0 mode, the status register can be read with the following timing.
• When a read status register command is issued and then an even address in the user ROM or
• When a program command, a block erase command, or a block blank check command is
Table 21.6 Status Register
[Legend]
SR0 to SR7: Status register data
D0 to D7:
Note: The FMERSF (SR5) and FMPRSF (SR4) bits are cleared to 0 by a clear status register
Page 1096 of 1372
Bits in Status
Register
SR0 (D0)
SR1 (D1)
SR2 (D2)
SR3 (D3)
SR4 (D4)
SR5 (D5)
SR6 (D6)
SR7 (D7)
data flash is read
issued and then an even address in the user ROM or data flash is read before a read array
command is issued
command.
When the FMERSF (SR5) or FMPRSF (SR4) bit is 1, the program, block erase, and block
blank check commands are not accepted.
Status Register
Data bus from which the bit is read when a read status register command is issued.
Bits in
FMLSTR
FMPRSF
FMERSF
FMRDY
Status Name
Reserved
Reserved
Reserved
Reserved
Programming
status
Erase status
Reserved
Sequencer status Busy
0
Completed
successfully
Completed
successfully
Status
H8S/2426, H8S/2426R, H8S/2424 Group
1
Ended with
error
Ended with
error
Ready
REJ09B0466-0350 Rev. 3.50
Value after
Reset
0
0
1
Jul 09, 2010

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