R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 280

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.8
In the H8S/2426R Group, external address space areas 2 to 5 can be designated as continuous
synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous
DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous
DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Synchronous DRAM of CAS latency 1 to 4 can be connected.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
6.8.1
Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to
RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and
synchronous DRAM space is shown in table 6.8. Possible synchronous DRAM interface settings
are and continuous area (areas 2 to 5).
Table 6.8
With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE
signal. The OE pin of the DRAM is used as the CKE signal, and the CS5 pin is used as
synchronous DRAM clock (SDRAMφ). The bus specifications for continuous synchronous
DRAM space conform to the settings for area 2. The pin wait and program wait for the continuous
synchronous DRAM are invalid.
Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and
address-precharge-setting command (Precharge-sel) output on the upper column addresses.
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RMTS2
0
1
Group.
Synchronous DRAM Interface
Setting Continuous Synchronous DRAM Space
RMTS1
0
1
0
1
Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM
Space
RMTS0
0
1
0
1
0
1
1
Area 5
Normal space
Normal space
DRAM space
Continuous synchronous DRAM space
Mode settings of synchronous DRAM
Reserved (setting prohibited)
Continuous DRAM space
Area 4
Normal space
Normal space
DRAM space
H8S/2426, H8S/2426R, H8S/2424 Group
Area 3
Normal space
DRAM space
DRAM space
REJ09B0466-0350 Rev. 3.50
Area 2
DRAM space
DRAM space
DRAM space
Jul 09, 2010