R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 910

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
15.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ in normal serial communication interface mode and Smart Card interface
mode.
Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0)
Page 880 of 1372
Bit
7
6
Bit Name
TDRE
RDRF
Serial Status Register (SSR)
1
0
Initial Value
R/W
R/(W) *
R/(W) *
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0. Exercise care because if reception of the
next data is completed while the RDRF flag is set
to 1, an overrun error occurs and receive data will
be lost.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR,
and data writing to TDR is enabled.
When 0 is written to TDRE after reading
TDRE = 1
When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
When serial reception ends normally and
receive data is transferred from RSR to RDR
When 0 is written to RDRF after reading
RDRF = 1
When the DMAC or DTC is activated by an
RXI interrupt and transferred data from RDR
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010