R4F24269NVFQV Renesas Electronics America, R4F24269NVFQV Datasheet - Page 433

• Manufacturer Part Number: R4F24269NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24269NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
(3)
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfers and internal
accesses (on-chip memory or internal I/O registers) are executed in parallel.
• Write data buffer function and DMAC register setting
• Write data buffer function and next DMAC operation
(4)
If the last transfer cycle is for an internal address, note that even if low-level output at the TEND
pin has been set, a low level may not be output at the TEND pin under the following external bus
conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed
in parallel.
1. EXDMAC cycle*
2. Write cycle with write buffer mode enabled
3. DMAC single address cycle for a different channel with write buffer mode enabled
4. Bus release cycle
5. CBR refresh cycle
Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2
above.
If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in
synchronization with the bus cycle.
However, if the last transfer cycle and a CBR refresh*
the CBR refresh*
low in this case for the refresh cycle*
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
If the setting of a register that controls external accesses is changed during execution of an
external access by means of the write data buffer function, the external access may not be
performed normally. Registers that control external accesses should only be manipulated when
external reads, etc., are used with DMAC operation disabled, and the operation is not
performed in parallel with external access.
The DMAC can start its next operation during external access using the write data buffer
function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are
different from the case in which the write data buffer function is disabled. Also, internal bus
cycles maybe hidden, and not visible.
Write Data Buffer Function
TEND Output
2
and the last transfer cycle may be executed consecutively, TEND may also go
1
2
.
2
occur simultaneously, note that although
Section 7 DMA Controller (DMAC)
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