HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 12

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.3
6.4
6.5
6.6
6.7
6.8
6.9
Rev. 4.00 Jan 26, 2006 page x of xxii
6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 141
6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 142
6.2.12 Address Control Register (ADRCR)
Operation .......................................................................................................................... 144
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Basic Bus Interface ........................................................................................................... 152
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
DRAM Interface ............................................................................................................... 165
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation.................................................................................................... 174
6.5.11 Refresh Control.................................................................................................... 180
6.5.12 Examples of Use .................................................................................................. 184
6.5.13 Usage Notes ......................................................................................................... 188
Interval Timer ................................................................................................................... 191
6.6.1
Interrupt Sources............................................................................................................... 197
Burst ROM Interface......................................................................................................... 197
6.8.1
6.8.2
6.8.3
Idle Cycle .......................................................................................................................... 199
6.9.1
6.9.2
(Provided Only in Flash Memory R Version and Mask ROM Versions) ............ 143
Area Division ....................................................................................................... 144
Bus Specifications................................................................................................ 147
Memory Interfaces ............................................................................................... 148
Chip Select Signals .............................................................................................. 148
Address Output Method....................................................................................... 150
Overview.............................................................................................................. 152
Data Size and Data Alignment............................................................................. 152
Valid Strobes........................................................................................................ 153
Memory Areas ..................................................................................................... 154
Basic Bus Control Signal Timing ........................................................................ 156
Wait Control ........................................................................................................ 163
Overview.............................................................................................................. 165
DRAM Space and RAS Output Pin Settings ....................................................... 165
Address Multiplexing........................................................................................... 167
Data Bus............................................................................................................... 167
Pins Used for DRAM Interface............................................................................ 168
Basic Timing........................................................................................................ 168
Precharge State Control ....................................................................................... 170
Wait Control ........................................................................................................ 171
Byte Access Control and CAS Output Pin........................................................... 172
Operation ............................................................................................................. 191
Overview.............................................................................................................. 197
Basic Timing........................................................................................................ 197
Wait Control ........................................................................................................ 198
Operation ............................................................................................................. 199
Pin States in Idle Cycle ........................................................................................ 202