HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 570

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 Smart Card Interface
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used in combination with the SDIR bit to communicate with inverse-convention
cards. *
section 14.3.4, Register Settings.
Bit 2
SINV
0
1
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0
SMIF
0
1
Notes: 1. The function for switching between LSB-first and MSB-first mode can also be used
Rev. 4.00 Jan 26, 2006 page 546 of 938
REJ09B0276-0400
2
2. The data logic level inversion function can also be used with the normal serial
The SINV bit does not affect the logic level of the parity bit. For parity settings, see
with the normal serial communication interface. Note that when the communication
format data length is set to 7 bits and MSB-first mode is selected for the serial data to
be transferred, bit 0 of TDR is not transmitted, and only bits 7 to 1 of the received data
are valid.
communication interface. Note that, when inverting the serial data to be transferred,
parity transmission and parity checking is based on the number of high-level periods at
the serial data I/O pin, and not on the register value.
Description
Unmodified TDR contents are transmitted
Receive data is stored unmodified in RDR
Inverted TDR contents are transmitted
Receive data is inverted before storage in RDR
Description
Smart card interface function is disabled
Smart card interface function is enabled
(Initial value)
(Initial value)