HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 515

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2
TEIE
0
1
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,
Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): The function of these bits differs for the normal
serial communication interface and for the smart card interface. Their function is switched with
the SMIF bit in SCMR.
For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the
SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings
of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or
serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits . For further details on selection of the SCI clock source, see table 13.9 in
section 13.3, Operation.
Bit 1
CKE1
0
0
1
1
Notes: 1. Initial value
then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing
the TEIE bit to 0.
Bit 0
CKE0 Description
0
1
0
1
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Description
Transmit-end interrupt requests (TEI) are disabled*
Transmit-end interrupt requests (TEI) are enabled*
Internal clock, SCK pin available for generic input/output *
Internal clock, SCK pin used for clock output *
External clock, SCK pin used for clock input *
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input *
External clock, SCK pin used for serial clock input
Internal clock, SCK pin used for serial clock output *
Internal clock, SCK pin used for serial clock output
Section 13 Serial Communication Interface
Rev. 4.00 Jan 26, 2006 page 491 of 938
REJ09B0276-0400
3
3
2
(Initial value)
1
1