HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 840

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Registers
Rev. 4.00 Jan 26, 2006 page 816 of 938
REJ09B0276-0400
FLMSR-Flash Memory Status Register
Bit
Initial value
R/W
Note: This register is used only in the flash memory and flash memory R versions. Reading the
RAM select, RAM2, RAM1
Notes 1.
corresponding address in a mask ROM version will always return 1s, and writes to this address
are disabled.
FLER
Bit 7
0
1
FLER
R
0
7
2.
3.
Flash memory program/erase protection (error protection) is disabled (Initial value)
[Clearing condition]
WDT reset, reset via the RES pin or hardware standby mode
An error has occurred during flash memory programming/erasing, and error pro-
tection*
[Setting conditions]
1. Flash memory was read*
2. A hardware exception-handling sequence (other than a reset, invalid instruction,
3. The SLEEP instruction (including software standby mode) was executed during
See 18.6.3, Error Protection, for details.
The read value in this case is undefined.
Before stack and vector read by exception handling.
or instruction fetch, but not including reading of a RAM area overlapped onto
flash memory).
trap instruction, or zero-divide exception) was executed just before programming
or erasing.*
programming or erasing.
1
6
1
is enabled
3
5
1
2
4
while being programmed or erased (including vector
1
Reserved bits
Description
3
1
H'EE07D
2
1
1
1
Flash Memory
0
1