HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 95

IC H8 MCU FLASH 128K 100-QFP

HD64F3067RF20

Manufacturer Part Number
HD64F3067RF20
Description
IC H8 MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3067RF20

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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3.6
Figure 3.1 to 3.3 show a memory maps of the H8/3067, H8/3066, and H8/3065. The address space
is divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and on-chip registers differ between the 64-kbyte mode
(mode 6), the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5).
The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8
and @aa:16) also differs.
3.6.1
The H8/3067 Group memory map includes reserved areas to which read/write access is prohibited.
Note that normal operation is not guaranteed if the following reserved areas are accessed.
(1) The reserved area in the internal I/O register space
(2) Other reserved areas
In modes 1 to 5 in the H8/3065, there is a reserved area in area 7 as shown in figure 3.3.
The H8/3067 Group internal I/O register space includes a reserved area to which access is
prohibited. For details see Appendix B, Internal I/O Registers.
In mode 5 in the H8/3066 and H8/3065, there is a reserved area in area 0 as shown in figures
3.2 and 3.3.
Memory Map in Each Operating Mode
Note on Reserved Areas
Rev. 4.00 Jan 26, 2006 page 71 of 938
Section 3 MCU Operating Modes
REJ09B0276-0400

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