HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 585

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Receiving Serial Data: Data reception in smart card mode uses the same processing procedure as
for the normal SCI. Figure 14.8 shows a sample reception processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the ORER flag and PER flag are cleared to 0 in SSR. If either is set, perform the
3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1.
4. Read the receive data from RDR.
5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2.
1. Data write
2. Transfer from TDR to TSR
3. Serial data output
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
I/O data
TXI (TEND
interrupt)
appropriate receive error handling, then clear both the ORER and the PER flag to 0.
transmission, D0 in MSB-first transmission) of the retransmit data to be transmitted next has
been completed.
Figure 14.6 Relation Between Transmit Operation and Internal Registers
Ds
In case of normal transmission: TEND flag is set
In case of transmit error:
Da
Figure 14.7 Timing of TEND Flag Setting
Db
Dc
Data 1
Data 1
Data 1
TDR
Dd
De
12.5 etu
11.0 etu
Df
ERS flag is set
Steps 2 and 3 above are repeated until the
TEND flag is set.
(shift register)
Dg
Data 1
TSR
Rev. 4.00 Jan 26, 2006 page 561 of 938
Dh
Dp
Section 14 Smart Card Interface
Data remains in TDR
Data 1
Guard time
DE
REJ09B0276-0400
I/O signal
output
When GM = 0
When GM = 1