HD64F3067RF20 Renesas Electronics America, HD64F3067RF20 Datasheet - Page 13

• Manufacturer Part Number: HD64F3067RF20
• Description: IC H8 MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3067RF20

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.10 Bus Arbiter........................................................................................................................ 203
6.11 Register and Pin Input Timing .......................................................................................... 206
Section 7 DMA Controller
7.1
7.2
7.3
7.4
7.5
7.6
6.10.1 Operation ............................................................................................................. 203
6.11.1 Register Write Timing ......................................................................................... 206
6.11.2 BREQ Pin Input Timing ...................................................................................... 207
Overview........................................................................................................................... 209
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode) .............................................................. 214
7.2.1
7.2.2
7.2.3
7.2.4
Register Descriptions (2) (Full Address Mode) ................................................................ 220
7.3.1
7.3.2
7.3.3
7.3.4
Operation .......................................................................................................................... 229
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 257
7.4.11 NMI Interrupts and DMAC.................................................................................. 258
7.4.12 Aborting a DMAC Transfer................................................................................. 259
7.4.13 Exiting Full Address Mode.................................................................................. 260
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode ......................... 261
Interrupts ........................................................................................................................... 262
Usage Notes ...................................................................................................................... 263
7.6.1
Features................................................................................................................ 209
Block Diagram ..................................................................................................... 210
Functional Overview............................................................................................ 211
Input/Output Pins ................................................................................................. 212
Register Configuration......................................................................................... 212
Memory Address Registers (MAR) ..................................................................... 214
I/O Address Registers (IOAR) ............................................................................. 215
Execute Transfer Count Registers (ETCR).......................................................... 215
Data Transfer Control Registers (DTCR) ............................................................ 217
Memory Address Registers (MAR) ..................................................................... 220
I/O Address Registers (IOAR) ............................................................................. 220
Execute Transfer Count Registers (ETCR).......................................................... 221
Data Transfer Control Registers (DTCR) ............................................................ 223
Overview.............................................................................................................. 229
I/O Mode.............................................................................................................. 231
Idle Mode............................................................................................................. 233
Repeat Mode ........................................................................................................ 236
Normal Mode....................................................................................................... 240
Block Transfer Mode ........................................................................................... 243
DMAC Activation................................................................................................ 248
DMAC Bus Cycle ................................................................................................ 250
Multiple-Channel Operation ................................................................................ 256
Note on Word Data Transfer................................................................................ 263
................................................................................................ 209
Rev. 4.00 Jan 26, 2006 page xi of xxii