DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 13

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.4
4.5
4.6
4.7
4.8
4.9
Section 5 Interrupt Controller ..............................................................................91
5.1
5.2
5.3
5.4
5.5
5.6
5.7
4.3.2
4.3.3
Traces................................................................................................................................... 81
Address Error ....................................................................................................................... 82
4.5.1
4.5.2
Interrupts.............................................................................................................................. 84
4.6.1
4.6.2
Instruction Exception Handling ........................................................................................... 85
4.7.1
4.7.2
4.7.3
Stack Status after Exception Handling................................................................................. 88
Usage Note........................................................................................................................... 89
Features................................................................................................................................ 91
Input/Output Pins ................................................................................................................. 93
Register Descriptions ........................................................................................................... 93
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Interrupt Sources................................................................................................................ 107
5.4.1
5.4.2
Interrupt Exception Handling Vector Table....................................................................... 109
Interrupt Control Modes and Interrupt Operation .............................................................. 113
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
CPU Priority Control Function Over DTC and DMAC..................................................... 122
Interrupts after Reset............................................................................................... 78
On-Chip Peripheral Functions after Reset Release ................................................. 79
Address Error Source.............................................................................................. 82
Address Error Exception Handling ......................................................................... 83
Interrupt Sources..................................................................................................... 84
Interrupt Exception Handling ................................................................................. 84
Trap Instruction....................................................................................................... 85
Sleep Instruction Exception Handling .................................................................... 86
Exception Handling by Illegal Instruction .............................................................. 87
Interrupt Control Register (INTCR) ....................................................................... 94
CPU Priority Control Register (CPUPCR) ............................................................. 95
Interrupt Priority Registers A to C, E to I, K, and L
(IPRA to IPRC, IPRE to IPRI, IPRK, and IPRL) ................................................... 97
IRQ Enable Register (IER) ..................................................................................... 99
IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 101
IRQ Status Register (ISR)..................................................................................... 105
Software Standby Release IRQ Enable Register (SSIER) .................................... 106
External Interrupts ................................................................................................ 107
Internal Interrupts ................................................................................................. 108
Interrupt Control Mode 0 ...................................................................................... 113
Interrupt Control Mode 2 ...................................................................................... 115
Interrupt Exception Handling Sequence ............................................................... 117
Interrupt Response Times ..................................................................................... 118
DTC and DMAC Activation by Interrupt ............................................................. 119
Rev. 2.00 Jun. 28, 2007 Page xi of xxiv