DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 344

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
8.3
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC
activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt
source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer
(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding DTCER bit is cleared.
8.4
Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information can be located in either short address mode
(three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies
either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see
section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is
shown in figure 8.2
The DTC reads the start address of transfer information from the vector table according to the
activation source, and then reads the transfer information from the start address. Figure 8.3 shows
correspondences between the DTC vector address and transfer information.
Rev. 2.00 Jun. 28, 2007 Page 318 of 864
REJ09B0341-0200
Start
address
Chain
transfer
Activation Sources
Location of Transfer Information and DTC Vector Table
MRA
MRB
MRA
MRB
in short address mode
Transfer information
0
CRA
CRA
Lower addresses
1
4 bytes
SAR
DAR
DAR
SAR
Figure 8.2 Transfer Information on Data Area
2
CRB
CRB
3
Transfer information
for the 2nd transfer
in chain transfer
(3 longwords)
Transfer information
for one transfer
(3 longwords)
Start
address
Chain
transfer
MRA MRB
MRA MRB
0
Transfer information
in full address mode
CRA
CRA
Lower addresses
1
4 bytes
SAR
DAR
SAR
DAR
Reserved
Reserved
2
(0 write)
(0 write)
CRB
CRB
3
Transfer
information
for the 2nd
transfer
in chain transfer
(4 longwords)
Transfer
information
for one transfer
(4 longwords)