DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 16

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.14 Bus Arbitration .................................................................................................................. 227
6.15 Bus Controller Operation in Reset ..................................................................................... 229
6.16 Usage Notes ....................................................................................................................... 230
Section 7 DMA Controller (DMAC)................................................................. 233
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Section 8 Data Transfer Controller (DTC)........................................................ 307
8.1
Rev. 2.00 Jun. 28, 2007 Page xiv of xxiv
6.14.1 Operation .............................................................................................................. 227
6.14.2 Bus Transfer Timing............................................................................................. 228
Features.............................................................................................................................. 233
Input/Output Pins............................................................................................................... 236
Register Descriptions......................................................................................................... 237
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
Transfer Modes .................................................................................................................. 258
Operations.......................................................................................................................... 259
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 Bus Cycles in Dual Address Mode ....................................................................... 284
7.5.11 Bus Cycles in Single Address Mode..................................................................... 293
DMA Transfer End ............................................................................................................ 298
Relationship among DMAC and Other Bus Masters ......................................................... 300
7.7.1
7.7.2
Interrupt Sources................................................................................................................ 302
Notes on Usage .................................................................................................................. 305
Features.............................................................................................................................. 307
DMA Source Address Register (DSAR) .............................................................. 238
DMA Destination Address Register (DDAR) ...................................................... 239
DMA Offset Register (DOFR).............................................................................. 240
DMA Transfer Count Register (DTCR) ............................................................... 241
DMA Block Size Register (DBSR) ...................................................................... 242
DMA Mode Control Register (DMDR)................................................................ 243
DMA Address Control Register (DACR)............................................................. 252
DMA Module Request Select Register (DMRSR) ............................................... 258
Address Modes ..................................................................................................... 259
Transfer Modes..................................................................................................... 262
Activation Sources................................................................................................ 267
Bus Modes ............................................................................................................ 269
Extended Repeat Area Function ........................................................................... 270
Address Update Function using Offset ................................................................. 272
Register during DMA Transfer............................................................................. 277
Priority of Channels.............................................................................................. 282
DMA Basic Bus Cycle.......................................................................................... 283
CPU Priority Control Function Over DMAC ....................................................... 300
Bus Arbitration among DMAC and Other Bus Masters ....................................... 301