DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 643

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• At power-on
• At mode switching
To secure the appropriate clock duty cycle simultaneously with power-on, use the following
procedure.
1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a
2. Fix the SCK pin to the specified output using the CKE1 bit in SCR.
3. Set SMR and SCMR to enable smart card interface mode.
 At transition from smart card interface mode to software standby mode
 At transition from smart card interface mode to software standby mode
pull-up or pull-down resistor.
Set the CKE0 bit in SCR to 1 to start clock output.
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK
2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously,
3. Write 0 to the CKE0 bit in SCR to stop the clock.
4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the
5. Make the transition to software standby mode.
1. Clear software standby mode.
2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the
pin to the values for the output fixed state in software standby mode.
set the CKE1 bit to the value for the output fixed state in software standby mode.
specified level with the duty cycle retained.
appropriate duty cycle is then generated.
[1] [2] [3]
Normal operation
Figure 14.32 Clock Stop and Restart Procedure
[4] [5]
Software
standby
[6]
Section 14 Serial Communication Interface (SCI)
[7]
Rev. 2.00 Jun. 28, 2007 Page 617 of 864
Normal operation
REJ09B0341-0200