DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 196

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
(6)
Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area
5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that
the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in
SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an
external address space. For details, see section 3, MCU Operating Modes.
When area 5 external address space is accessed, the CS5 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in
SRAMCR. Table 6.12 shows the external interface of area 5.
Table 6.12 Area 5 External Interface
(7)
Area 6 includes internal I/O registers. In external extended mode, area 6 other than on-chip I/O
register area is external address space.
When area 6 external address space is accessed, the CS6 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 6 by the MPXE6 bit in MPXCR and the BCSEL6 bit in
SRAMCR. Table 6.13 shows the external interface of area 6.
Rev. 2.00 Jun. 28, 2007 Page 170 of 864
REJ09B0341-0200
Interface
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
Area 5
Area 6
MPXE5 of MPXCR
0
0
1
1
Register Setting
BCSEL5 of SRAMCR
0
1
0
1