UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 325

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(9) Capture operation
(10) Edge detection
(11) Timer operation
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(a) When valid edge of TI000 is specified as count clock
(b) Pulse width to accurately capture value by signals input to TI010 and TI000 pins
(c) Generation of interrupt signal
(d) Note when CRC001 (bit 1 of capture/compare control register 00 (CRC00)) is set to 1
(a) Specifying valid edge after reset
(b) Sampling clock for eliminating noise
The signal input to the TI000/TI010 pin is not acknowledged while the timer is stopped, regardless of the operation
mode of the CPU.
Remark f
When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as
a trigger does not operate correctly.
To accurately capture the count value, the pulse input to the TI000 and TI010 pins as a capture trigger must be
wider than two count clocks selected by PRM00 (refer to Figure 6-7).
The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM000 and
INTTM010) are generated at the rising edge of the next count clock (refer to Figure 6-7).
When the count value of the TM00 register is captured to the CR000 register in the phase reverse to the signal
input to the TI000 pin, the interrupt signal (INTTM000) is not generated after the count value is captured. If the
valid edge is detected on the TI010 pin during this operation, the capture operation is not performed but the
INTTM000 signal is generated as an external interrupt signal. Mask the INTTM000 signal when the external
interrupt is not used.
If the operation of the 16-bit timer/event counter 00 is enabled after reset and while the TI000 or TI010 pin is at
high level and when the rising edge or both the edges are specified as the valid edge of the TI000 or TI010 pin,
then the high level of the TI000 or TI010 pin is detected as the rising edge. Note this when the TI000 or TI010
pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled
again.
The sampling clock for eliminating noise differs depending on whether the valid edge of TI000 is used as the
count clock or capture trigger. In the former case, the sampling clock is fixed to f
selected by PRM00 is used for sampling.
When the signal input to the TI000 pin is sampled and the valid level is detected two times in a row, the valid
edge is detected. Therefore, noise having a short pulse width can be eliminated (refer to Figure 6-7).
PRS
: Peripheral hardware clock frequency
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
PRS
. In the latter, the count clock
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