UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 434

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UPD78F0551MA-FAA-AX

Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0551MA-FAA-AX

Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
<R>
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
ADPC0 Register
Analog I/O
selection
Digital I/O
selection
Remark ADPC0:
ADPC0 Register
Analog input
selection
Digital I/O
selection
PM2:
OPAMP0E: Bit 7 of operational amplifier 0 control register (AMP0M)
PGAEN:
ADS:
Input mode
Output mode
Input mode
Output mode
PM2 Register
Table 12-6. Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin
Table 12-7. Setting Functions of P23/ANI3 to P27/ANI7 Pins
A/D port configuration register 0
Port mode register 2
Bit 6 of AMP0M
Analog input channel specification register
Input mode
Output mode
Input mode
Output mode
0
0
1
1
0
1
0
1
OPAMP0E
PM2 Register
bit
0
1
0
1
PGAEN bit
Selects ANIn.
Does not select ANIn.
Selects ANIn.
Does not select ANIn.
Selects ANIn.
Does not select ANIn.
ADS Register(n = 3 to 7)
Selects ANI1.
Does not select ANI1.
Selects PGAOUT.
Selects ANI1.
Does not select
PGAOUT and ANI1.
Selects ANI1.
Does not select ANI1.
Selects PGAOUT.
Selects ANI1.
Does not select
PGAOUT and ANI1.
Selects ANI1.
Does not select ANI1.
Selects ANI1.
Does not select ANI1.
ADS Register
Analog input (to be converted into
digital signals)
Analog input (not to be converted
into digital signals)
Setting prohibited
Setting prohibited
Digital input
Setting prohibited
Digital output
P23/ANI3 to P27/ANI7 Pins
Analog input (to be converted into digital
signals)
Analog input (not to be converted into
digital signals)
PGA input (PGA output is converted into
digital signals)
PGA input (to be converted into digital
signals)
PGA input (not to be converted into digital
signals)
Operational amplifier 0 output (to be
converted into digital signals)
Operational amplifier 0 output (not to be
converted into digital signals)
Operational amplifier 0 output and PGA
input (PGA output is converted into digital
signals)
Operational amplifier 0 output (to be
converted into digital signals)
Operational amplifier 0 output (not to be
converted into digital signals)
Setting prohibited
Setting prohibited
Digital input
Setting prohibited
Setting prohibited
Digital output
Setting prohibited
CHAPTER 12 A/D CONVERTER
P21/ANI1/AMP0OUT/PGAIN Pin
420

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