UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 581

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UPD78F0551MA-FAA-AX

Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0551MA-FAA-AX

Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Address: FF80H After reset: 00H R/W
CSIM10
Notes 1.
Caution Be sure to clear bit 5 to 0.
Symbol
Figure 16-4. Format of Serial Operation Mode Register 10 (CSIM10) (78K0/KB2-L and 78K0/KC2-L)
2.
3.
4.
5.
6.
TRMD10
DIR10
Bit 0 is a read-only bit.
To use P10/SCK10 and P12/SO10 as general-purpose ports, set CSIM10 in the default status (00H).
Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.
Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication).
The SO10 output (refer to Figure 16-1) is fixed to the low level when TRMD10 is 0. Reception is started
when data is read from SIO10.
Do not rewrite DIR10 when CSOT10 = 1 (during serial communication).
CSOT10
CSIE10
CSIE10
0
<7>
Note 5
0
1
1
0
1
0
1
Note 6
Note 4
Disables operation
Enables operation
Receive mode (transmission disabled).
Transmit/receive mode
MSB
LSB
Communication is stopped.
Communication is in progress.
TRMD10
6
Note 1
Note 2
5
0
and asynchronously resets the internal circuit
Operation control in 3-wire serial I/O mode
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
DIR10
4
Transmit/receive mode control
Communication status flag
First bit specification
3
0
2
0
Note 3
.
1
0
CSOT10
0
567

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