UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 818

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
3rd Edition
Remark “Classification” in the above table classifies revisions as follows.
Edition
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d):
Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Modification of Table 12-6 Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin
Modification of <4> in 12.4.1 Basic operations of A/D converter
Modification of Table 12-8 Resistance and Capacitance Values of Equivalent Circuit
(Reference Values)
Addition of the analog input channel specification register (ADS) to Table 13-1
Configuration of Operational Amplifier
Addition of (3) Analog input channel specification register (ADS) to 13.3 Registers
Used in Operational Amplifier
Modification of Table 13-5 Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin
Addition of the port output mode register 6 (POM6) to Table 14-1 Configuration of Serial
Interface UART6
Addition of (9) Port output mode register 6 (POM6) to 14.3 Registers Controlling
Serial Interface UART6
Addition of the port output mode register 6 (POM6) to 14.4.2 (1) Registers used
Modification of (1) 78K0/KY2-L and 78K0/KA2-L in Table 14-2 Relationship Between
Register Settings and Pins
Addition of Caution 3 to Figure 15-3 Format of IICA Shift Register (IICA)
Addition of Note 3 to, and modification of Caution in Figure 15-5 Format of IICA Control
Register 0 (IICACTL0) (1/4)
Addition of description of the SPIE0 bit to Figure 15-5 Format of IICA Control Register 0
(IICACTL0) (2/4)
Modification of description of the STT0 bit in Figure 15-5 Format of IICA Control
Register 0 (IICACTL0) (3/4)
Modification of Caution in Figure 15-5 Format of IICA Control Register 0 (IICACTL0)
(4/4)
Modification of Figure 15-6 Format of IICA Status Register 0 (IICAS0) (2/3)
Partial deletion of description in 15.3 (9) Port mode register 6 (PM6)
Modification of 15.4.2 Setting transfer clock by using IICWL and IICWH registers
Modification of (C) External maskable interrupt (INTKR) in Figure 17-1 Basic
Configuration of Interrupt Function
Addition of Note to 19.2.1 (2) (b) Release by reset signal generation
Modification of Figure 19-4 HALT Mode Release by Reset
Addition of Note 1 to Figure 19-5 Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
Addition of Note 2 to (3) When internal high-speed oscillation clock is used as CPU
clock in Figure 19-6 STOP Mode Release by Interrupt Request Generation
Addition of Note to 19.2.2 (2) (b) Release by reset signal generation
Modification of Figure 19-7 STOP Mode Release by Reset
Modification of Figure 20-1 Block Diagram of Reset Function to Figure 20-4 Timing of
Reset in STOP Mode by RESET Input
Description
APPENDIX C REVISION HISTORY
CHAPTER 12 A/D
CONVERTER
CHAPTER 13
OPERATIONAL
AMPLIFIERS
CHAPTER 14
SERIAL INTERFACE
UART6
CHAPTER 15
SERIAL INTERFACE
IICA
CHAPTER 17
INTERRUPT
FUNCTIONS
CHAPTER 19
STANDBY FUNCTION
CHAPTER 20 RESET
FUNCTION
Chapter
(7/8)
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