UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 681

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(1) When LVI is OFF upon power application (option byte: LVISTART = 0)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(when X1 oscillation
oscillation clock (f
Internal high-speed
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (refer to CHAPTER 22
Remark V
V
V
Internal reset signal
system clock (f
POR
PDR
= 1.61 V (TYP.)
= 1.59 V (TYP.)
Supply voltage
High-speed
is selected)
1.8 V
2.
3.
4.
CPU
(V
XH
V
Note 1
IH
LOW-VOLTAGE DETECTOR).
V
V
0 V
Operation
LVI
DD
)
)
The operation guaranteed range is 1.8 V ≤ V
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.), input a
low level to the RESET pin before the voltage reaches to 1.8 V.
The internal voltage stabilization wait time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal high-speed oscillation clock, high-speed system clock or subsystem clock can be selected as
the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation
stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the
stabilization time.
LVI
POR
PDR
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
)
stops
:
: POC power supply fall detection voltage
: POC power supply rise detection voltage
LVI detection voltage
Wait for oscillation
accuracy stabilization
(102 to 407 s)
specified by software
0.5 V/ms (MIN.)
Starting oscillation is
(0.93 to 3.7 ms)
Wait for voltage
Reset processing
stabilization
(12 to 51 s)
Note 2
Note 3
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
and Low-Voltage Detector (1/2)
Note 4
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
(102 to 407 s)
used for interrupt
Reset processing
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
DD
Starting oscillation is
specified by software
≤ 5.5 V. To make the state at lower than 1.8 V reset state
(12 to 51 s)
Note 4
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
(102 to 407 s)
Reset processing
Wait for voltage
(0.93 to 3.7 ms)
specified by software
Starting oscillation is
stabilization
(12 to 51 s)
Note 3
used for reset
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
Note 4
Operation stops
667