UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 518

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(8) Port output mode register 6 (POM6)
(9) Port mode register 6 (PM6)
This register sets the output mode of P60 to P63 in 1-bit units. During I
1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61 to 0,
and set the output latches of P60 and P61 to 1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Address: FF2AH
Note
Symbol
POM6
Symbol
Address: FF26H
PM6
78K0/KC2-L only
Remark
POM6n
PM6n
7
0
0
1
7
1
After reset: 00H
0
1
Figure 15-12. Format of Port Output Mode Register 6 (POM6)
The figure shown above presents the format of port mode register 6 of the 78K0/KC2-L. For
the format of port mode register 6 of other products, refer to (1) Port mode registers (PMxx)
in 4.3 Registers Controlling Port Function.
After reset: FFH
Normal output (CMOS output) mode
N-ch open drain output (V
Output mode (output buffer on)
Input mode (output buffer off)
Figure 15-13. Format of Port Mode Register 6 (PM6)
6
0
6
1
R/W
1
5
5
0
R/W
P6n pin I/O mode selection (n = 0 to 3)
P6n pin output mode selection (n = 0 to 3)
DD
tolerance) mode
1
4
4
0
PM63
POM63
3
3
CHAPTER 15 SERIAL INTERFACE IICA
Note
2
C communication, set POM60 and POM61 to
PM62
POM62
2
2
Note
PM61
1
POM61
1
PM60
0
POM60
0
504