CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 113
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
11.3.2
Power On Reset (POR) occurs every time the power to
the device is switched on. POR is released when the
supply is typically 2.2V +/-12% for the upward supply
transition, with typically 120mV of hysterisis during the
power on transient. Bit 4 of the Status and Control Regis-
ter (CPU_SCR) is set to record this event (the register
contents are set to 00010000 by the POR). After a POR,
the microprocessor is suspended for 64 ms. This pro-
vides time for the Vcc supply to stabilize after the POR
11.3.3
The following diagram illustrates the sequence of events
(in time) for execution reset, from voltage stabilization on
through execution of user’s code. Once voltage trips
POR and after 64 ms, the CPU starts boot calibration.
Boot calibration takes 2,502 cycles, with the CPU run-
ning at 3 MHz. This results in approximately 800 µ s for
11.3.4 External Reset (X
Pulling the X
the microcontroller to perform a Power On Reset (POR).
The X
operation and can be tied directly to ground, or left open.
11.3.5 Watchdog Timer Reset (WDR)
The user has the option to enable the WDT. The WDT is
enabled by clearing the PORS bit. Once the PORS bit is
cleared, the Watchdog Timer (WDT) cannot be disabled.
September 5, 2002
res
pin does not require a pull-down resistor for
res
Power On Reset (POR)
Execution Reset
POR 2.2V ± 12%
T
pin high for a minimum of 10 µS forces
rVdd
64 ms
Calibration
res
Start CPU
2502
3 MHz
Boot
)
3.0V (Good)
~
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Figure 30: Execution Reset
boot.asm
Vector
Reset
User Code
trip, before CPU operation begins. If the Vcc voltage
drops below the POR downward supply trip point (2.1V
+/-12%, once the internal reference is established), POR
is reasserted.
Important : The PORS status bit is set at POR and can
only be cleared by the user, and cannot be set by firm-
ware.
the time between beginning boot calibration and reset
vector. At reset vector, the boot.asm must execute
before user code begins running. (boot.asm contains
device configurations from PSoC Designer. The time it
takes boot.asm to execute varies depending on device
configuration settings such as CPU speed.)
The only exception to this is if a POR event takes place,
which will disable the WDT.
The sleep timer is used to generate the sleep time period
and the watchdog time period. The sleep timer divides
down the 32K system clock, and thereby produces the
sleep time period. The user can program the sleep time
period to be one of 4 multiples of the period of the 32K
clock. When the sleep time elapses (sleep timer over-
flows), an interrupt to the Sleep Timer Interrupt Vector
will be generated.
Special Features of the CPU
V
3.0 - 5.5
cc
Power
113