CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 72
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
10.2
Table 61:
10.3
72
ACLK0
ACLK1
Acolumn0
Acolumn1
Acolumn2
Acolumn3
Signal
Analog System Clocking Signals
Array of Analog PSoC Blocks
Analog System Clocking Signals
A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK0[2:0] bits in the Analog Clock Select Register (CLK_CR1).
A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected
by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be
muxed into this line using the ACLK1[2:0] bits in the Analog Clock Select Register (CLK_CR1).
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 0. This signal is
derived from the muxed input of the 24V1 , 24V2 , ACLK0 , and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn0[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 1. This signal is
derived from the muxed input of the 24V1 , 24V2 , ACLK0 , and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4.The
Acolumn1[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 2. This signal is
derived from the muxed input of the 24V1 , 24V2 , ACLK0 , and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn2[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
A system-clocking signal that can drive all analog PSoC blocks in Analog Column 3. This signal is
derived from the muxed input of the 24V1 , 24V2 , ACLK0 , and ACLK1 system clock signals. The output
of this mux is then passed through a 1:4 divider to reduce the frequency by a factor of 4. The
Acolumn3[1:0] bits in the CLK_CR0 Register determine the selected Column Clock.
Column 0
Analog
ACA00
ASA10
ASB20
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Figure 16: Array of Analog PSoC Blocks
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Column 1
ASA21
Analog
ACA01
ASB11
Definition
Column 2
Analog
ACA02
ASA12
ASB22
Column 3
Analog
ACA03
ASB13
ASA23
September 5, 2002