CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 121
![no-image](/images/manufacturer_photos/0/1/179/cypress_semiconductor_corp_sml.jpg)
CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
11.10.1 Data File Read
The user’s data file should be read into the programmer.
The checksum should be calculated by the programmer
for each record and compared to the record checksum
stored in the file for each record. If there is an error, a
message should be sent to the user explaining that the
file has a checksum error and the programming should
not be allowed to continue.
11.10.2 Programmer Flow
The following sequence (with descriptions) is the main
flow used to program the devices: (Note that failure at
any step will result in termination of the flow and an error
message to the device programmer’s operator.)
11.10.2.1
The silicon ID is read and verified against the expected
value. If it is not the expected value, then the device is
failed and an error message is sent to the device pro-
grammer’s operator.
This test will detect a bad connection to the programmer
or an incorrect device selection on the programmer.
The silicon ID test is required to be first in the flow and
cannot be bypassed. The sequence is as follows:
Set Vcc=0V
Set SDATA=HighZ
Set SCLK=VILP
Set Vcc=Vccp
Start the programmer’s SCLK driver
“free running”
WAIT-AND-POLL
ID-SETUP
WAIT-AND-POLL
READ-ID-WORD
Notes : See “DC Specifications“ table in section 13 for
value of Vccp and VILP. See “AC Specifications” table in
section 13 for value of frequency for the SCLK driver
(Fsclk).
11.10.2.2
The Flash memory is erased. This is accomplished by
the following sequence:
SET-CLK-FREQ(num_MHz_times_5)
September 5, 2002
Verify Silicon ID
Erase
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Erase All
WAIT-AND-POLL
11.10.2.3
The Flash is programmed with the contents of the user’s
programming file. This is accomplished by the following
sequence:
For num_block = 0 to max_data_block
For address =0 to 63
WRITE-BYTE(address,data):
End for address loop
SET-CLK-FREQ(num_MHz_times_5)
SET-BLOCK-NUM(num_block)
PROGRAM-BLOCK
WAIT-AND-POLL
End for num_block loop
11.10.2.4
The device data is read out to compare to the data in the
user’s programming file. This is accomplished by the fol-
lowing sequence:
For num_block = 0 to max_data_block
SET-BLOCK-NUM (num_block)
VERIFY-SETUP
Wait & POLL the SDATA for a high to
low transition
For address =0 to max_byte_per_block
READ-BYTE(address,data)
End for address loop
End for num_block loop
Note : This should be done 2 times; once at Vcc=Vcclv
and once at Vcc=Vcchv.
11.10.2.5
The security operation protects certain blocks from being
read or changed. This is done at the end of the flow so
that the security does not interfere with the verify step.
Security is set with the following sequence:
For address =0 to 63
WRITE-SECURITY-BYTE(address,data):
End for address loop
SET-CLK-FREQ(num_MHz_times_5)
SECURE
WAIT-AND-POLL
Note : This sequence is done at Vcc=Vccp.
Program
Verify (at Low Vcc and High Vcc)
Set Security
Special Features of the CPU
121