CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 47
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
8.6
GPIO Interrupts are polarity configurable and pin-wise
maskable (within each Port’s pin configuration registers).
They all share the same interrupt priority and vector.
Any general purpose I/O can be used as an interrupt
source. The GPIO bit in the General Interrupt Mask Reg-
ister (INT_MSK0) must be set to enable pin interrupts, as
well as the enable bits for each pin, which are located in
For a GPIO interrupt to occur, the following steps must
be taken:
1.
2.
3.
4.
5.
September 5, 2002
The pin Drive Mode must be set so the pin can be
an input.
The pin must be enabled to generate an interrupt by
setting the appropriate bit in the Port interrupt
Enable Register (PRTxIE).
The edge type for the interrupt must be set in the
Port Interrupt Control 0 and Control 1 Registers
(PRTxIC0 and PRTxIC1). Edge type must be set to
a value other than 00.
The GPIO bit must be set in the General Interrupt
Mask Register (INT_MSK0).
The Global Interrupt Enable bit must be set.
GPIO Interrupt
PIN
Int Logic
PORTX IE Register
(PRT0IE...PRT5IE)
GPIO Cell
GPIO BIT IE
Figure 11: GPIO Interrupt Enable Diagram
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
All GPIO INTOUTs
INTOUTn
the Port x Interrupt Enable Registers (PRTxIE). There
are user selectable options to generate an interrupt on 1)
any change from the last read state, 2) rising edge, and
3) falling edge.
When Interrupt on Change is selected, the state of the
GPIO pin is stored when the port is read. Changes from
this state will then assert the interrupt, if enabled.
6.
Because the GPIO interrupts all share the same
interrupt vector, the source for the GPIO interrupt
must be cleared before any other GPIO interrupt will
occur (i.e., the OR gate in
the INTOUTn signals together). If any of the
INTOUTn signals are high, the flip-flop in
11
OR
will not see a rising edge and no IRQ will occur.
“1”
D
R
BIT S, INT_MSK0
GPIO Int Enable
Q
IRQ
FigureTitle 11
Decode Logic
To Priority
“ors” all of
FigureTitle
Interrupts
47