CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 29
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
5.0
5.1
Up to five 8-bit-wide I/O ports (P0-P4) and one 4-bit wide
I/O port (P5) are implemented. The number of general
purpose I/Os implemented and connected to pins
depends on the individual part chosen. All port bits are
independently programmable and have the following
capabilities:
S
S
S
S
S
S
Port 1, pin 0 is used in conjunction with device Test
Mode and will not function as an output for approxi-
mately 16 ms after X
will be held low for approximately 16 ms. This does not
prevent the CPU from writing to this Data Register bit
(PRT0DR, bit 0). However, the written data will not
appear on the output pin until after the 16 ms delay.
There are no restrictions when using the pin as an input.
In addition, the pin may also be configured (e.g., drive
September 5, 2002
General-purpose digital input readable by the CPU.
General-purpose digital output writable by the CPU.
Independent control of data direction for each port
bit.
Independent access for each port bit to Global Input
and Global Output busses.
Interrupt programmable to assert on rising edge,
falling edge, or change from last pin state read.
Output drive strength programmable in logic 0 and 1
states as strong, resistive (pull-up or pull-down), or
high impedance.
I/O Ports
Introduction
RES
. After negating X
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
RES
, the pin
strength, interrupts) during this time. A device reset with
Power On Reset (POR) will not exhibit this problem
because there is a CPU hold-off time of approximately
64 ms before code execution begins.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is main-
tained on a capacitor.
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leak-
age to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is com-
pared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.
Port 0 and Port 2 have additional analog input and/or
analog output capability. The specific routing and multi-
plexing of analog signals is shown in the following dia-
gram:
I/O Ports
29