CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 44
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
8.2
The interrupt controller contains a separate flip-flop for
each interrupt. When an interrupt is generated, it is regis-
tered as a pending interrupt. It will stay pending until it is
serviced, a reset occurs, or there is a write to the
INT_VC Register. A pending interrupt will only generate
an interrupt request when enabled by the appropriate
mask bit in the Digital PSoC Block Interrupt Mask Regis-
ter (INT_MSK1) or General Interrupt Mask Register
(INT_MSK0), and the Global IE bit in the CPU_F register
is set.
Additionally, for GPIO Interrupts, the appropriate enable
and interrupt-type bits for each I/O pin must be set (see
section 6.0,
and
rupts, the interrupt source must be set (see section
and
During the servicing of any interrupt, the MSB and LSB
of Program Counter and Flag registers (CPU_PC and
CPU_F) are stored onto the program stack by an auto-
matic CALL instruction (13 cycles) generated during the
interrupt acknowledge process. The user firmware may
preserve and restore processor state during an interrupt
using the PUSH and POP instructions. The memory ori-
ented CPU architecture requires minimal state saving
during interrupts, providing very fast interrupt context
switching. The Program Counter and Flag registers
(CPU_PC and CPU_F) are restored when the RETI
instruction is executed. If two or more interrupts are
pending at the same time, the higher priority interrupt
(lower priority number) will be serviced first.
After a copy of the Flag Register is stored on the stack,
the Flag Register is automatically cleared. This disables
all interrupts, since the Global IE flag bit is now cleared.
Executing a RETI instruction restores the Flag register,
and re-enables the Global Interrupt bit.
Nested interrupts can be accomplished by re-enabling
interrupts inside an interrupt service routine. To do this,
set the IE bit in the Flag Register. The user must store
sufficient information to maintain machine state if this is
done.
44
Table 76 on page
Table 34 on page
Interrupt Control Architecture
Table 29 on page
99).
34). For Analog Column Inter-
31,
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Table 33 on page
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
10.11
33,
Each digital PSoC block has its own unique Interrupt
Vector and Interrupt Enable bit. There are also individual
interrupt vectors for each of the Analog columns, Supply
Voltage Monitor, Sleep Timer and General Purpose I/Os.
8.3
Table 43:
The interrupt process vectors the Program Counter to
the appropriate address in the
Typically, these addresses contain JMP instructions to
the start of the interrupt handling routine for the interrupt.
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
Address
Interrupt Vectors
10
11
12
13
14
15
Interrupt Vector Table
1
2
3
4
5
6
7
8
9
Supply Monitor Interrupt Vector
DBA00 PSoC Block Interrupt Vector
DBA01 PSoC Block Interrupt Vector
DBA02 PSoC Block Interrupt Vector
DBA03 PSoC Block Interrupt Vector
DCA04 PSoC Block Interrupt Vector
DCA05 PSoC Block Interrupt Vector
DCA06 PSoC Block Interrupt Vector
DCA07 PSoC Block Interrupt Vector
Acolumn 0 Interrupt Vector
Acolumn 1 Interrupt Vector
Acolumn 2 Interrupt Vector
Acolumn 3 Interrupt Vector
GPIO Interrupt Vector
Sleep Timer Interrupt Vector
On-Chip Program Memory Starts
Description
Interrupt Vector Table
September 5, 2002
.