CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 42
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
7.2.3
All digital PSoC block clocks are a user-selectable
choice of 48M , 24V1 , 24V2 , or 32K , as well as clocking
signals from other digital PSoC blocks or general pur-
8.0
8.1
Interrupts can be generated by the General Purpose I/O
lines, the Power monitor, the internal Sleep Timer, the
eight Digital PSoC blocks, and the four analog columns.
Every interrupt has a separate enable bit, which is con-
tained
(INT_MSK0) and the Digital PSoC Block Interrupt Mask
Register (INT_MSK1). When the user writes a “1” to a
particular bit position, this enables the interrupt associ-
ated with that position. There is a single Global Interrupt
Enable bit in the Flags Register (CPU_F), which can dis-
able all interrupts, or enable those interrupts that also
have their individual interrupt bit enabled. During a reset,
the enable bits in the General Interrupt Mask Register
(INT_MASK0), the enable bits in the Digital PSoC Block
Interrupt Mask Register (INT_MSK1) and the Global
Interrupt Enable bit in the Flags Register (CPU_F) are all
cleared. The Interrupt Vector Register (INT_VC) holds
the interrupt vector for the highest priority pending inter-
rupt when read, and when written will clear all pending
interrupts.
If there is only one interrupt pending and an instruction is
executed that would mask that pending interrupt (by
clearing the corresponding bit in either of the interrupt
mask registers at address E0h or E1h in Bank 0), the
CPU will take that interrupt. Since the pending interrupt
has been cleared and there are no others, the resulting
interrupt vector is 0000h and the CPU will jump to the
user code at the beginning of Flash. To address this
issue, use the macro defined in m8c.inc called
"M8C_DisableIntMask" in PSoC Designer. This macro
brackets the register write with a disable then an enable
of global interrupts.
42
in
Interrupts
Overview
the
Digital PSoC Block Clocking Options
General
Interrupt
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Mask
Register
pose I/O pins. There are a total of 16 possible clock
options for each digital PSoC block. See the Digital
PSoC Block section for details.
September 5, 2002