CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 23
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
Examples :
2.3.5
The result of an instruction using this addressing mode is
placed within either the RAM memory space or the regis-
ter space. Operand 1 is added to the X register forming
the address that points to the location of the result. The
source for the instruction is the A register. Arithmetic
instructions require two sources, the second source is
the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are two
bytes in length.
Table 17:
Example :
2.3.6
The result of an instruction using this addressing mode is
placed within either the RAM memory space or the regis-
ter space. Operand 1 is the address of the result. The
September 5, 2002
ADD
MOV
ADD [X+7],
Instruction
Opcode
[7],
REG[8], A
Destination Indexed
Destination Direct Immediate
Destination Indexed
Destination Index
A
A
;In this case, the value
;in the memory location
;at address X+7 is added
;with the Accumulator,
;and the result is placed
;in the memory location
;at address x+7. The
;Accumulator is
;unchanged.
Operand 1
;In this case, the
;value in the memory
;location at address
;7 is added with the
;Accumulator, and the
;result is placed in
;the memory location
;at address 7. The
;Accumulator is
;unchanged.
;In this case, the
;Accumulator is moved
;to the register
;space location at
;address 8. The
;Accumulator is
;unchanged.
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
source for the instruction is Operand 2, which is an
immediate value. Arithmetic instructions require two
sources, the second source is the location specified by
Operand 1. Instructions using this addressing mode are
three bytes in length.
Table 18:
Examples :
2.3.7
The result of an instruction using this addressing mode is
placed within either the RAM memory space or the regis-
ter space. Operand 1 is added to the X register to form
the address of the result. The source for the instruction is
Operand 2, which is an immediate value. Arithmetic
instructions require two sources, the second source is
the location specified by Operand 1 added with the X
register. Instructions using this addressing mode are
three bytes in length.
Table 19:
ADD [7],
MOV REG[8], 6
Instruction
Instruction
Opcode
Opcode
Destination Indexed Immediate
Destination Direct Immediate
Destination Indexed Immediate
Destination Address Immediate Value
Destination Index
5
Operand 1
Operand 1
;In this case, value in
;the memory location at
;address 7 is added to
;the immediate value of
;5, and the result is
;placed in the memory
;location at address 7.
;In this case, the
;immediate value of 6 is
;moved into the register
;space location at
;address 8.
Immediate Value
Operand 2
CPU Architecture
Operand 2
23