CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 25
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
Table 23:
2.4
September 5, 2002
0C
0D
3C
3D
0A
0B
0E
3A
3B
7A
7B
Note: Interrupt acknowledge to Interrupt Vector table = 13 cycles.
09
0F 10 3 ADC [X+expr], expr
01
02
03
04
05
06
07 10 3 ADD [X+expr], expr
38
21
22
23
24
25
26
27 10 3 AND [X+expr], expr
70
41
42 10 3 AND reg[X+expr], expr
64
65
66
67
68
69
39
73
78
79
30
74
75
9x 11 2 CALL
5 2 ADD SP, expr
4 2 AND A, expr
6 2 AND A, [expr]
7 2 AND A, [X+expr]
7 2 AND [expr], A
8 2 AND [X+expr], A
9 3 AND [expr], expr
4 2 AND F, expr
9 3 AND reg[expr], expr
4 1 ASL A
7 2 ASL [expr]
8 2 ASL [X+expr]
4 1 ASR A
7 2 ASR [expr]
8 2 ASR [X+expr]
5 2 CMP A, expr
7 2 CMP A, [expr]
8 2 CMP A, [X+expr]
8 3 CMP [expr], expr
9 3 CMP [X+expr], expr
4 1 CPL A
4 1 DEC A
4 1 DEC X
7 2 DEC [expr]
8 2 DEC [X+expr]
9 1 HALT
4 1 INC A
4 1 INC X
4 2 ADC A, expr
6 2 ADC A, [expr]
7 2 ADC A, [X+expr]
7 2 ADC [expr], A
8 2 ADC [X+expr], A
9 3 ADC [expr], expr
4 2 ADD A, expr
6 2 ADD A, [expr]
7 2 ADD A, [X+expr]
7 2 ADD [expr], A
8 2 ADD [X+expr], A
9 3 ADD [expr], expr
Instruction Set Summary
Instruction Format
Instruction Set Summary (Sorted by Mnemonic)
if (A<B) C=1
if (A=B) Z=1
Flags
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
7C 13 3 LCALL
7D
5C
5D
2C
2D
Ex
Cx
Dx
Bx
Ax
4F
5A
5B
5E
5F 10 3 MOV [expr], [expr]
3E 10 2 MVI A, [ [expr]++ ]
3F 10 2 MVI [ [expr]++ ], A
2A
2B
2E
2F 10 3 OR [X+expr], expr
76
77
Fx 13 2 INDEX
50
51
52
53
54
55
56
57
58
59
60
61
62
63
40
29
43
44 10 3 OR reg[X+expr], expr
71
8x
7 2 INC [expr]
8 2 INC [X+expr]
7 2 JACC
5 2 JC
5 2 JMP
5 2 JNC
5 2 JNZ
5 2 JZ
7 3 LJMP
4 1 MOV X, SP
4 2 MOV A, expr
5 2 MOV A, [expr]
6 2 MOV A, [X+expr]
5 2 MOV [expr], A
6 2 MOV [X+expr], A
8 3 MOV [expr], expr
9 3 MOV [X+expr], expr
4 2 MOV X, expr
6 2 MOV X, [expr]
7 2 MOV X, [X+expr]
5 2 MOV [expr], X
4 1 MOV A, X
4 1 MOV X, A
6 2 MOV A, reg[expr]
7 2 MOV A, reg[X+expr]
5 2 MOV reg[expr], A
6 2 MOV reg[X+expr], A
8 3 MOV reg[expr], expr
9 3 MOV reg[X+expr], expr
4 1 NOP
4 2 OR A, expr
6 2 OR A, [expr]
7 2 OR A, [X+expr]
7 2 OR [expr], A
8 2 OR [X+expr], A
9 3 OR [expr], expr
9 3 OR reg[expr], expr
4 2 OR F, expr
Instruction Format
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C, Z
Flags
C, Z
C, Z
Z
Z
Z
20
18
10
08
7E 10 1 RETI
7F
6A
6B
6C
28 11 1 ROMX
6D
6E
6F
19
1A
1B
1C
1D
1E
1F 10 3 SBB [X+expr], expr
00 15 1 SSC
11
12
13
14
15
16
17 10 3 SUB [X+expr], expr
4B
4C
4D
4E
47
48
49
4A 10 3 TST reg[X+expr], expr
72
31
32
33
34
35
36
37 10 3 XOR [X+expr], expr
45
46 10 3 XOR reg[X+expr], expr
5 1 POP X
5 1 POP A
4 1 PUSH X
4 1 PUSH A
8 1 RET
4 1 RLC A
7 2 RLC [expr]
8 2 RLC [X+expr]
4 1 RRC A
7 2 RRC [expr]
8 2 RRC [X+expr]
4 2 SBB A, expr
6 2 SBB A, [expr]
7 2 SBB A, [X+expr]
7 2 SBB [expr], A
8 2 SBB [X+expr], A
9 3 SBB [expr], expr
4 2 SUB A, expr
6 2 SUB A, [expr]
7 2 SUB A, [X+expr]
7 2 SUB [expr], A
8 2 SUB [X+expr], A
9 3 SUB [expr], expr
5 1 SWAP A, X
7 2 SWAP A, [expr]
7 2 SWAP X, [expr]
5 1 SWAP A, SP
8 3 TST [expr], expr
9 3 TST [X+expr], expr
9 3 TST reg[expr], expr
4 2 XOR F, expr
4 2 XOR A, expr
6 2 XOR A, [expr]
7 2 XOR A, [X+expr]
7 2 XOR [expr], A
8 2 XOR [X+expr], A
9 3 XOR [expr], expr
9 3 XOR reg[expr], expr
Instruction Format
CPU Architecture
Flags
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
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