CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 52
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
Digital Communications Type A Block 06 Input Register
Digital Communications Type A Block 07 Input Register
The Data/Enable source select [3:0] bits select between
multiple inputs to the Digital PSoC Blocks. These inputs
serve as Clock Enables or Data Input depending on the
Digital PSoC Block’s programmed function. If “Chain
Function to Previous” data input is selected for Data/
Enable then the selected Digital PSoC block receives its
Data, Enable, Zero Detect, and all chaining information
from the previous digital PSoC block. The data inputs
that are selected from the GPIO pins (through the Global
Input Bus) are synchronized to the 24 MHz clock. The
following table shows the function dependent meaning of
the data input.
Table 49:
9.2.3
The digital PSoC block’s outputs can be selected to drive
associated Global Output Bus signals via the Output
Select bits. In addition, the output drive can be selec-
tively enabled in this register. The SPI Slave has an aux-
iliary input which is also controlled by selections in this
register.
52
Timer
Counter
CRC
PRS
Deadband
TX UART
RX UART
SPI Master
SPI Slave
Function
Digital Function Data Input Definitions
Digital Basic Type A / Communications Type A Block xx Output Register
Positive Edge Capture
Count Enable (Active High)
Data Input
N/A
Kill Signal (Active High)
N/A
RX Data In
MISO (Master In/Slave Out)
MOSI (Master Out/Slave In)
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Data Input
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
The Clock[3:0] bits select multiple sources for the clock
for each digital PSoC block. The sources for each digital
PSoC block clock are selected from the Global Input
Bus, System Clocks, and other neighboring digital PSoC
blocks. As shown in the table, Digital PSoC Blocks 0-3
can interface to Global I/Os 00-03, and Digital PSoC
block 04-07 can interface to Global I/Os 4-7. It is impor-
tant to note that clock inputs selected from the GPIO pins
(through the Global Input Bus) are not synchronized.
This may cause indeterminate results if the CPU reads a
block register as it is changing in response to an external
clock. CPU reads must be manually synchronized, either
through the block interrupt, or through a multiple read
and voting scheme.
(DCA06IN, Address = Bank 1, 39h)
(DCA07IN, Address = Bank 1, 3Dh)
September 5, 2002