CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 69
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
If the SPI Master block is being used to receive data,
“dummy” bytes must be written to the TX Data Register
in order to initiate transmission/reception of each byte.
9.5.8.3
MISO (master-in, slave-out) is selected by the input mul-
tiplexer. The clock input multiplexer selects a clock that
runs at twice the desired data rate. The SPIM function
divides the input clock by 2 to obtain the 50% duty-cycle
required for proper timing. The input multiplexer is con-
trolled by the PSoC block Input Register (DCA04IN-
DCA07IN).
9.5.8.4
There are two outputs, both of which can be enabled
onto the Global Output bus. The MOSI (master-out,
slave-in) data line provides the output serial data. The
second output is the bit-clock derived by dividing the
input clock by 2 to ensure a 50% duty-cycle. The PSoC
block Output Register (DCA04OU-DCA07OU) controls
output options.
Note : The SPIM function does not provide the SS_ sig-
nal that may be used by a corresponding SPI Slave.
However, this can be implemented with a GPIO pin and
supporting firmware if desired.
9.5.8.5
When enabled, the function generates an interrupt on TX
Reg Empty status (Data Register 1 empty). If Mode[1] in
the Function Register is set, the SPI Master will generate
an interrupt on SPI Complete.
9.5.8.6
1.
2.
September 5, 2002
Reading the Status
Reading Control Register 0, which contains the sta-
tus bits, automatically resets the status bits to 0 with
the exception of TX Reg Empty, which is cleared
when a byte is written to the TX Data Register (Data
Register 1), and the RX Reg Full, which is cleared
when a byte is read from the RX Data Register
(Data Register 2).
Using Interrupts
TX Reg Empty status or optionally SPI Complete
status generates the block interrupt. Executing the
Inputs
Outputs
Interrupts
Usage Notes
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
9.5.9
9.5.9.1
The SPI Slave function provides a full-duplex bi-direc-
tional synchronous data transceiver that requires an
externally provided bit clock for the data. This function
requires a Digital Communications Type PSoC block. It
cannot be chained for longer data words. This Digital
Communications Type PSoC block supports SPI modes
for 0, 1, 2, and 3. See
supported modes.
9.5.9.2
Data Register 0 provides a shift register for both incom-
ing and outgoing data. Output data is written to Data
Register 1 (TX Data Register). Input data is read from
Data Register 2 (RX Data Register). When Data Register
0 is empty, its value is updated from Data Register 1. As
new data bits are shifted in, the transmit bits are shifted
out. After the 8 bits are transmitted and received by Data
Register 0, the received byte is transferred into Data
Register 2 from which it can be read. Simultaneously, the
next byte to transmit, if available, is transferred from
Data Register 1 into Data Register 0. Control Register 0
(DCA04CR0-DCA07CR0) provides status information
and configures the function for one of the four standard
modes, which configure the interface based on clock
polarity and phase with respect to data.
9.5.9.3
The SPIS function has three inputs. The Input Register
(DCA04IN-DCA07IN) controls the input multiplexer,
which selects the MOSI data stream. It also controls the
clock selection multiplexer from which the function
obtains the master’s bit clock. The AUX-IO bits of the
Output Register (DCA04OU-DCA07OU) select a Global
Input signal from which the SS_ (Slave Select) signal is
obtained. It is important to note that the SS_ signal can
interrupt routine does not automatically clear status.
If SPI Complete is selected as the interrupt source,
Control Register 0 (status) must be read in the inter-
rupt routine to clear the status. If TX Reg Empty sta-
tus is selected, a byte must be written to the TX
Data Register (Data Register 1) to clear the status. If
the interrupting status is not cleared further inter-
rupts will be suppressed.
SPI Slave - Serial Peripheral Interface
(SPIS)
Summary
Registers
Inputs
FigureTitle 15
for waveforms of the
Digital PSoC Blocks
69