CY8C26233-24PVI Cypress Semiconductor Corp, CY8C26233-24PVI Datasheet - Page 119
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CY8C26233-24PVI
Manufacturer Part Number
CY8C26233-24PVI
Description
IC MCU 8K FLASH 256B 20-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ CY8C26xxxr
Datasheet
1.CY8C25122-24PI.pdf
(148 pages)
Specifications of CY8C26233-24PVI
Core Processor
M8C
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.25 V
Data Converters
A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Applications
CapSense
Technology
CMOS
Processing Unit
Microcontroller
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Package Type
SSOP
Screening Level
Industrial
Pin Count
20
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
428-1426
428-1426-5
428-1426
428-1426-5
428-1426
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C26233-24PVI
Manufacturer:
CY
Quantity:
431
Table 97:
1.
2.
3.
4.
5.
Notes :
NA: Not applicable
*: Indeterminate
Blk ID: Number of 64-byte block within FLASH memory space
Clock: CPU system clocking signal value
Pointer: Address of first byte of 64-byte block within SRAM memory space
TV: Table value
September 5, 2002
Reset
Read Block
Write Block
Erase Block
Protect Block
Erase All
Table Read
Checksum
Calibrate
Operation
This is a software-only reset.
This operation should only be invoked by calling a function in the FlashBlock library. Device specifications are no
longer guaranteed if this function is directly called by the user’s code .
This function can only be invoked by the device programmer, not by user’s code.
The address is hard coded by algorithm.
User-writeable registers include Main Oscillator Trim (IMO_TR), Internal Low Speed Oscillator Trim (ILO_TR), and
Bandgap Trim (BDG_TR).
1
3
5
2
3
CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM)
Calibrates
then sets
PC and SP
values to 0
Move block
of 64 bytes
of FLASH
data into
SRAM
Program
block of
FLASH with
data from
SRAM
Erase block
of FLASH
Set memory
protection
bits
Erase all
FLASH data
Read device
type code
Calculate
FLASH
checksum
for data
range speci-
fied
Sets user-
writable reg-
isters to
default
Function
4
00
01
02
03
04
05
06
07
08
NA
3Ah
3Ah
3Ah
3Ah
3Ah
3Ah
3Ah
3Ah
F8h
NA
SP
+3
SP
+3
SP
+3
SP
+3
SP
+3
SP
+3
SP
+3
SP
+3
F9h
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
NA
Blk
ID
Blk
ID
Blk
ID
NA
NA
Tbl
ID
Blk
Cou
nter
NA
FAh
Input SRAM Data
Pointer
Pointer
FBh
NA
NA
NA
NA
NA
NA
NA
Clock
Clock
Clock
Clock
FCh
NA
NA
NA
NA
NA
FDh
NA
0
0
0
0
0
NA
0
NA
0
0
0
0
0
NA
0
FEh
NA
0
0
0
0
0
NA
0
FFh
*
0
0
0
0
0
TV
(0)
CS
H
0
F8h
*
0
0
0
0
0
TV
(1)
CSL
0
F9h
Output SRAM Data
*
*
*
*
*
*
TV
(2)
*
*
FAh
Special Features of the CPU
*
*
*
*
*
*
TV
(3)
*
*
FBh
FCh
*
*
*
*
*
*
TV
(4)
*
*
*
*
*
*
*
*
TV
(5)
*
*
FDh
FEh
*
*
*
*
*
*
TV
(6)
*
*
119
*
*
*
*
*
*
TV
(7)
*
*
FFh