MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 112

• Manufacturer Part Number: MC68HC908GP32CP
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock Generator Module (CGMC)
Technical Data
110
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
Modulating the voltage on the CGM/XFC pin changes the frequency
within this range. By design, f
frequency, f
factor, E, or (L × 2
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
programmable modulo reference divider, which divides f
factor, R. The divider’s output is the final reference clock, CGMRDV,
running at a frequency, f
(30 kHz–100 kHz), always set R = 1 for specified performance. With an
external high-frequency clock source, use R to divide the external
frequency to between 30 kHz and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
fed back through a programmable prescale divider and a programmable
modulo divider. The prescaler divides the VCO clock by a power-of-two
factor P and the modulo divider reduces the VCO clock by a factor, N.
The dividers’ output is the VCO feedback clock, CGMVDV, running at a
frequency, f
more information.)
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGM/XFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
condition based on this comparison.
Clock Generator Module (CGMC)
RDV
NOM
VDV
7.4.4 Acquisition and Tracking
. The circuit determines the mode of the PLL and the lock
, (38.4 kHz) times a linear factor, L, and a power-of-two
= f
E
VCLK
)f
NOM
/(N × 2
RDV
.
VRS
= f
P
RCLK
). (See
MC68HC908GP32
is equal to the nominal center-of-range
RCLK
/R. With an external crystal
, and is fed to the PLL through a
7.4.6 Programming the PLL
Modes. The value of the
•
MC68HC08GP32
RCLK
MOTOROLA
by a
VCLK
VRS
—
.
Rev. 6
, is
for