MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 75

• Manufacturer Part Number: MC68HC908GP32CP
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.3.3.2 COP Reset
4.3.3.3 Low-Voltage Inhibit Reset
4.3.3.4 Illegal Opcode Reset
MC68HC908GP32
MOTOROLA
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MC68HC08GP32
A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the system integration module
(SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI
An LVI reset:
An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the
STOP instruction causes an illegal opcode reset.
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Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to the LVI
Drives the RST pin low for as long as V
voltage and during the oscillator stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay
Sets the LVI bit in the SIM reset status register
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Rev. 6
Resets and Interrupts
tripf
tripr
voltage.
voltage
DD
is below the LVI
Resets and Interrupts
Technical Data
tripr
Resets
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