MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 125

• Manufacturer Part Number: MC68HC908GP32CP
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.6.1 PLL Control Register
MC68HC908GP32
MOTOROLA
NOTE:
•
MC68HC08GP32
Address:
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Interrupt Flag Bit
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Reset:
Read:
Write:
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
—
$0036
PLLIE
Bit 7
Rev. 6
0
Clock Generator Module (CGMC)
Figure 7-4. PLL Control Register (PCTL)
= Unimplemented
PLLF
6
0
PLLON
5
1
BCS
4
0
PRE1
3
0
Clock Generator Module (CGMC)
PRE0
2
0
CGMC Registers
VPR1
1
0
Technical Data
VPR0
Bit 0
0
123