MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 233

• Manufacturer Part Number: MC68HC908GP32CP
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.7.1 Port E Data Register
MC68HC908GP32
MOTOROLA
NOTE:
•
MC68HC08GP32
Function:
Address:
Alternate
The port E data register contains a data latch for each of the two port E
pins.
PTE1 and PTE0 — Port E Data Bits
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. See
RxD — SCI Receive Data Input
TxD — SCI Transmit Data Output
Reset:
Read:
Write:
PTE1 and PTE0 are read/write, software programmable bits. Data
direction of each port E pin is under the control of the corresponding
bit in data direction register E.
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O.
18. Serial Communications Interface Module
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O.
Section 18. Serial Communications Interface Module
—
$0008
Bit 7
Rev. 6
0
Figure 16-17. Port E Data Register (PTE)
Input/Output (I/O) Ports
= Unimplemented
6
0
5
0
Unaffected by reset
4
0
Table
3
0
16-6.
2
0
(SCI).
Input/Output (I/O) Ports
PTE1
RxD
See Section
1
Technical Data
(SCI).
See
PTE0
Bit 0
TxD
Port E
231