MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 134

• Manufacturer Part Number: MC68HC908GP32CP
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clock Generator Module (CGMC)
7.8.2 Stop Mode
7.8.3 CGMC During Break Interrupts
Technical Data
132
If the OSCSTOPENB bit in the CONFIG register is cleared (default),
then the STOP instruction disables the CGMC (oscillator and phase
locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,
and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If the OSCSTOPENB bit in the CONFIG register is set, then the phase
locked loop is shut off but the oscillator will continue to operate in stop
mode.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
Clock Generator Module (CGMC)
MC68HC908GP32
19.8.3 SIM Break Flag Control
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MC68HC08GP32
MOTOROLA
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Rev. 6