HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 245
![IC H8 MCU FLASH 128K 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD64F3048BF25
Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3048BF25V.pdf
(903 pages)
Specifications of HD64F3048BF25
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 245 of 903
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DTCRB
DTCRB is initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit
enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is
enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the
CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further
information on operation in block transfer mode, see section 8.6.6, NMI Interrupts and Block
Transfer Mode.
DTME is set to 1 by reading the register while DTME = 0, then writing 1.
Bit 7: DTME
0
1
Bit
Initial value
Read/Write
Data transfer master enable
Enables or disables data
transfer, together with
the DTE bit, and is cleared
to 0 by an interrupt
DTME
R/W
Description
Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt occurs)
Data transfer is enabled
7
0
Reserved bit
R/W
6
0
Destination address
increment/decrement
Destination address
increment/decrement enable
These bits select whether
the destination address
register (MARB) is incremented,
decremented, or held fixed
during the data transfer
DAID
R/W
5
0
DAIDE
R/W
Transfer mode select
Selects whether the
block area is the source
or destination in block
transfer mode
4
0
Rev. 3.00 Sep 27, 2006 page 217 of 872
TMS
R/W
3
0
DTS2B
R/W
2
0
Data transfer select
2B to 0B
These bits select the data
transfer activation source
Section 8 DMA Controller
DTS1B
R/W
REJ09B0325-0300
1
0
(Initial value)
DTS0B
R/W
0
0
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