HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 463

IC H8 MCU FLASH 128K 100QFP

HD64F3048BF25

Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3048BF25

Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/PBF
Quantity:
2 631
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
11.3.4
Sample Setup Procedure for Non-Overlapping TPC Output
Figure 11.6 shows a sample procedure for setting up non-overlapping TPC output.
ITU setup
Port and
TPC setup
ITU setup
Figure 11.6 Setup Procedure for Non-Overlapping TPC Output (Example)
Non-Overlapping TPC Output
Select non-overlapping groups
Select TPC transfer trigger
Select counting operation
Set next TPC output data
Set next TPC output data
Select interrupt requests
Set initial output data
Enable TPC transfer
Select GR functions
Compare match A?
Set up TPC output
Non-overlapping
Set GR values
Start counter
TPC output
Yes
Section 11 Programmable Timing Pattern Controller
No
1
2
3
4
5
6
7
8
9
10
11
12
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
Enable the IMFA interrupt in TIER.
The DMAC can also be set up to transfer
data to the next data register.
Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
Set the NDER bits of the pins to be used for
TPC output to 1.
In TPCR, select the ITU compare match
event to be used as the TPC output trigger.
In TPMR, select the groups that will operate
in non-overlap mode.
Set the next TPC output values in the NDR
bits.
Set the STR bit to 1 in TSTR to start the timer
counter.
At each IMFA interrupt, write the next output
value in the NDR bits.
Rev. 3.00 Sep 27, 2006 page 435 of 872
REJ09B0325-0300

Related parts for HD64F3048BF25